The present invention relates to a semiconductor integrated circuit device having a plurality of operating speeds and a system using the device and, more particularly, to techniques effective when used in a multi-port memory used in an image processing technology and an image processing system using the same.
Generally speaking, the integrated circuit device for the digital signal processing is systematized according to its operating speeds. In case one system is to be prepared, its whole system is constructed by organically combining a variety of in-system integrated circuits having an identical operating speed.
In a multi-port random access; memory (which will be shortly referred to as the "multi-port" RAM), for example, a plurality of word lines and a plurality of data lines are connected with each memory cell so as to give one memory cell a plurality of input/output terminals (or I/O ports). In order to give a static memory cell two I/O ports, for example, two word lines and two pairs of complementary data lines are connected with one memory cell. In order to accomplish the write-in and read-out operations of each I/O port, moreover, two series of decoders and two series of read/write circuits are provided in a memory unit. These two series of decoders and read/write circuits are constructed to have a substantially equal operating speed. In other words, these two series of circuits are composed of CMOS (Complementary Metal Oxide Semiconductor) circuits.
In a color palette LSI (Large-scale Semiconductor Integrated circuit device) having a dual-port memory assembled therein, on the other hand, there are provided two products, one being composed of a CMOS circuit only whereas the other being composed of an ECL (Emitter Coupled Logic) circuit only. These two color palette LSIs are separately used according to the operating speeds of a system for processing an image to be formed.